1. Field of Invention
The present invention relates to a fabrication method for a shallow trench isolation region. More particularly, the present invention relates to a method for preventing void generation in a shallow trench isolation region.
2. Description of Related Art
The shallow trench isolation technique typically employs anisotropic etching to form a trench in a semiconductor substrate and filling an oxide material in the trench thereafter to form an isolation region for a device. The dimension of an isolation region formed by the shallow trench isolation technique can be adjusted. Further, the problem of bird's beak resulted in the conventional LOCOS is prevented. Therefore, shallow trench isolation is a preferred isolation technique in the sub-micron metal oxide semiconductor process.
Along with the increase of the integration of integrated circuits, the device dimension also gradually decreases. As the dimension of a shallow trench isolation region is being reduced when the integration of integrated circuits increases, problems that are associated with a high aspect ratio, for example, an incomplete filling of the trench or void generation in the subsequently formed shallow trench isolation region, will eventually surface. The isolation capability of a shallow trench isolation region would become inferior, leading to problems, such as, current leakage and undesirable reliability of the device.